AK7600 Datasheet, PDF (9/38 Pages) Asahi Kasei Microsystems – 2/6-Channel Audio CODEC with Digital EQ

[AK7600]
SWITCHING CHARACTERISTICS
(Ta=-40∼+85°C; AVDD=4.5~5.5V; DVDD=4.5∼5.5V; C_L=20pF; unless otherwise specified)
Parameter
Symbol
Min
typ
max
Master Clock Timing
Crystal Resonator
Frequency
fXTAL
10
13
MCKO Output
Frequency
fMCK
10
13
Duty cycle
dMCK
40
50
60
External Clock
256fsn:
fCLK
10
13
Pulse Width Low
tCLKL
36
Pulse Width High
tCLKH
36
MCKO Output
Frequency
fMCK
10
13
Duty cycle
dMCK
40
50
60
Audio Interface Timing (Master mode)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
fBCK
-
64fs
-
dBCK
-
50
-
tMBLR
−20
-
20
BICK “↓” to SDTO
tBSD
−20
-
20
Note 12. “L” when using I²C format.
Note 13. BICK rising edge must not occur at the same time as LRCK edge.
Units
MHz
MHz
%
MHz
ns
ns
MHz
%
Hz
%
ns
ns
Parameter
Symbol
min
typ
max Units
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
fSCL
-
400 kHz
Bus Free Time Between Transmissions
tBUF
1.3
-
μs
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
-
μs
Clock Low Time
tLOW
1.3
-
μs
Clock High Time
tHIGH
0.6
-
μs
Setup Time for Repeated Start Condition
tSU:STA
0.6
-
μs
SDA Hold Time from SCL Falling
(Note 14)
tHD:DAT
0
-
μs
SDA Setup Time from SCL Rising
tSU:DAT
0.1
-
μs
Rise Time of Both SDA and SCL Lines
tR
-
0.3
μs
Fall Time of Both SDA and SCL Lines
tF
-
0.3
μs
Setup Time for Stop Condition
tSU:STO
0.6
-
μs
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
50
ns
Capacitive load on bus
Cb
-
400
pF
Power-down & Reset Timing
PDN Pulse Width
(Note 15)
tPD
150
ns
Note 14. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 15. The AK7600 can be reset by bringing the PDN pin = “L”.
Note 16. I2C is a registered trademark of Philips Semiconductors.
MS0999-E-00
-9-
2008/09