AK7600 Datasheet, PDF (36/38 Pages) Asahi Kasei Microsystems – 2/6-Channel Audio CODEC with Digital EQ

[AK7600]
1. Grounding and Power Supply Decoupling
The AK7600 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually
supplied from the system’s analog supply. If AVDD and DVDD are supplied separately, the power-up sequence is not
critical. VSS1, VSS2, VSS3 and VSS4 of the AK7600 should be connected to the analog ground plane. System
analog ground and digital ground should be connected together near to where the supplies are brought onto the printed
circuit board. Decoupling capacitors should be as near to the AK7600 as possible, with the small value ceramic capacitor
being the nearest.
2. Voltage Reference Inputs
The input voltage to the VREFH pin sets the analog output range. Usually the VREFH pin is connected to AVDD and a
0.1μF ceramic capacitor is connected between AVDD and VSS1. VCOM is a signal ground of this chip (AVDD/2). The
electrolytic capacitor around 2.2µF attached between VCOM anVSS1 eliminates the effects of high frequency noise. The
ceramic capacitor in particular should be connected as close as possible to the pin. No load current may be taken from the
VCOM pin. All signals, especially clock, should be kept away from VREFH and VCOM in order to avoid unwanted
coupling into the AK7600.
3. Analog Inputs
The ADC inputs is single-ended and biased to VCOM voltage (AVDD/2) internally by 45kΩ(typ). The inputs signal
range scales with nominally at 0.65 x VREFH Vpp (typ)@fs=44.1kHz. The AK7600 can accept input voltage from VSS1
to AVDD. The output code format is 2's complement. Input DC offset is canceled by an integrated high-pass filter.
The AK7600 samples the analog input at 64fs(@fs=44.1kHz). A digital filter removes the noise over the stopband
attenuation level, except for a band of integral multiplication of 64fs. AK7600 has an integrated anti-alias RC filter in
order to reduce the noise at 64fs.
4. Analog output
The DAC output is single-ended and output range is 0.65xVREFH Vpp (typ) centered on VCOM. The bias voltage of the
external summing circuit is supplied externally. The input data format is two’s compliment. Positive full-scale output
corresponds to 7FFFFFH (@24bit) input code, Negative full scale is 800000H (@24bit) and VCOM voltage ideally is
000000H (@24bit). The Out-of-Band noise (shaping noise) generated by the internal delta-sigma modulator is attenuated
by an integrated switched capacitor filter (SCF) and a continuous time filter (CTF).
DC offsets on analog outputs are eliminated by AC coupling since analog outputs has DC offset of VCOM.
MS0999-E-00
- 36 -
2008/09