AK7600 Datasheet, PDF (16/38 Pages) Asahi Kasei Microsystems – 2/6-Channel Audio CODEC with Digital EQ

[AK7600]
■ Reset Function
When the RSTN bit = “0”, ADC and DAC parts of the AK7600 is powered down, but the internal register values are not
initialized. The analog outputs settle to VCOM and the DZF pins for both channels go to “H” or “L” depending on the
DZLH bit setting. SDTO1-3 pins go to “L” and analog output is VCOM voltage. Click noise occurs at this timing, mute
the analog output externally if the click noise (8) influences system application. Figure 13 shows the example of reset by
RSTN bit.
RSTN bit
Internal
RSTN(ADC)
Internal
RSTN(IIR)
Internal
RSTN(DAC)
ADC Internal
State
IIR Internal
State
DAC Internal
State
ADC In
(Analog)
SDTO1~3
DAC Out
(Analog)
Clock In
XTI(external)
Clock In
X'tal
DZF
4~5/fs(1)
~1/fs(2)
Normal Operation
Normal Operation
Normal Operation
GD(6)
8/fs (3
Power Down Init Cycl₎e
Normal Operation
7~8/fs (4)
Power Down Init
Normal Operation
1.5~2.5/fs (5)
Power Down Init
Normal Operation
GD(6)
"0" data(7)
GD(6) (9) (10)
(8)
(9)
(8)
Don't care(11)
GD(6)
9/fs
DZLH="0"(12)
Note:
(1) Internal RSTN will be “L”, 4~5/fs after RSTN bit went to “0”.
(2) ADC internal RSTN will be “H”, within 1/fs after RSTN bit = “1”.
(3) The reset cycle is 8/fs after ADC internal RSTN goes to “H”.
(4) Internal RSTN for IIR will be “H” after 7~8/fs from RSTN bit =“1”.
(5) Internal RSTN for DAC will be “H” after 1.5~2.5/fs from RSTN bit = “1”.
(6) The DAC and SDTO1-3 outputs corresponding to the ADC input has group delay (GD).
(7) SDTO1-3 output is “0” data when the AK7600 is in powered down mode.
(8) Click noise occurs when the initialization of ADC part is finished. Mute digital output if click noise adversely
affects system performance.
(9) Click noise occurs at the edge of internal RSTN.
(10) Analog output is VCOM voltage(AVDD/2) when RSTN bit = “0”.
(11) In case of inputting CLK from the XTI pin, the clock should be input before the RSTN bit is changed to “1” after
the RSTN bit is set to “0”.
(12) The DZF pin reflects the setting of DZLH bit. This pin changes to “L” or “H” 9/fs after the RSTN bit is set to “0”.
Figure 13. Reset Sequence Example
MS0999-E-00
- 16 -
2008/09