AK7600 Datasheet, PDF (15/38 Pages) Asahi Kasei Microsystems – 2/6-Channel Audio CODEC with Digital EQ

[AK7600]
■ System Reset
The AK7600 should be reset once by bringing the PDN pin = “L” upon power-up. The regulator will be powered-up by
inputting the master clock to the XTI pin directly or connect with a X’tal. The internal master clock starts by setting RSTN
bit to “1” after an interval of 10ms.
■ Power Down
The ADC and DAC parts of the AK7600 are placed in the power-down mode by bringing the PDN pin “L” and the digital
filter is also reset at the same time. The internal registers are initiated to their default value by the PDN pin = “L”. This
reset should always be made after power-up. In the power-down mode, SDTO1-3, BICK, LRCK and DZF pins go to “L”
and the analog output is VSS. When exiting the power-down mode, the AK7600 will be in reset state since the RSTN bit
= “0”. Figure 12 shows the power on/off sequence example.
PDN
Internal PDN
RSTN
Regulator
Internal ADC
State
Internal DAC
State
ADC In
(Analog)
SDTO1~3
DAC Out
(Analog)
Clock In
XTI(external)
Clock In
X'tal
DZF
Normal Operation
Normal Operation
Normal Operation
GD(4)
GD(4)
10ms(1)
(2)
Power Down
(3)
Power Down
Power Down
"0" data(5)
(7)
(6)
(8)
(9)
DZLH="1"
(10)
DZLH="0"
Note:
(1) After the PDN pin = “H”, the internal PDN is “L” until X’tal and regulator are powered-up. (Register writing is not
valid for 10ms of this period)
(2) During the RSTN bit is “0”, all circuits will be powered down except the regulator and X’tal even when the
internal PDN is “H”.
(3) Regulator will be powered-up after the PDN pin goes to “H”.
(4) The DAC and SDTO1-3 outputs corresponding to the ADC input has group delay (GD).
(5) The SDTP1-3 outputs are “0” when the AK7600 is powered-down.
(6) The DAC output is VSS voltage when the AK7600 is powered-down.
(7) Click noise occurs at the falling edge of PDN.
(8) In case of connecting a X’tal, the clock output is “L” when the PDN pin =“L”. The X’tal will be powered up after
the PDN pin =“H”.
(9) In power down mode(PDN pin = “L”), the DZF pin = “L”.
(10) The DZF pin output will reflects the DZLH bit setting when internal PDN is “H”.
Figure 12. Power Up/Down Sequence Example
MS0999-E-00
- 15 -
2008/09