AK7600 Datasheet, PDF (17/38 Pages) Asahi Kasei Microsystems – 2/6-Channel Audio CODEC with Digital EQ

[AK7600]
■I²C BUS INTERFACE (Microcontroller Interface)
Access to the AK7600 registers and RAM is processed by I²C bus. The format of the I²C is complement with fast mode
(max: 400kHz). The AK7600 does not support Hs mode. (max: 3.4MHz).
■ Data Transfer
In order to access any IC devices on the I²C BUS, input a start condition first, followed by a single Slave address
which includes the Device Address. IC devices on the BUS compare this Slave address with their own addresses
and the IC device which has an identical address with the Slave-address generates an acknowledgement. An IC
device with the identical address then executes either a read or a write operation. After the command execution,
input a Stop condition.
1-1. Data Change
Change the data on the SDA line while SCL line is “L”. SDA line condition must be stable and fixed while the
clock is “H”. Change the Data line condition between “H” and “L” only when the clock signal on the SCL line is
“L”. Change the SDA line condition while SCL line is “H” only when the start condition or stop condition is input.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 14. Data Transition
1-2. Start condition and Stop condition
Start condition is generated by the transition of “H” to “L” on the SDA line while the SCL line is “H”. All
instructions are initiated by Start condition. Stop condition is generated by the transition of “L” to “H” on SDA
line while SCL line is “H”. All instructions end by Stop condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 15. Start Condition and Stop Condition
MS0999-E-00
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2008/09