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AK4352 Datasheet, PDF (9/13 Pages) Asahi Kasei Microsystems – 2V & LOW POWER MULTI-BIT DAC | |||
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ASAHI KASEI
[AK4352]
LRCK
BICK
SDATA
16bit
SDATA
18bit
Lch
Rch
15 14
17 16
10
Donât
care
15 14
10
Donât
care
15
Donât
3 2 1 0 care 17 16
3
21
0
Donât
care
17
* BICK needs 32fs or 36fs or more than 36fs.
Figure 4. Mode 3 Timing
n De-emphasis filter
The AK4352 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. This filter corresponds to 44.1kHz
sampling. The de-emphasis is enabled by setting DEM pin âHâ.
n Power-down
The AK4352 is placed in the power-down mode by bringing PD pin âLâ and the anlog outputs are floating(Hi-Z).
Figure 5 shows an example of the system timing at the power-down and power-up.
PD
Internal
State
D/A In
(Digital)
D/A Out
(Analog)
Clock In
MCLK,LRCK,BICK
Normal Operation
Power-down
Normal Operation
â0âdata
GD (1)
(3) (2)
(3)
GD (1)
(4)
External
Mute
(5)
Mute On
Figure 5. Power-down/up sequence example
Notes:
(1) Analog output corresponding to digital input have the group delay (GD).
(2) Analog outputs are floating(Hi-Z) at the power-down mode.
(3) Click noise occures at the edges(ââ ââ) of the falling edge of PD signal.
(4) When the external clocks(MCLK,BICK,LRCK) are stopped, the AK4352 should be in the power-down
mode.
(5) Please mute the analog output externally if the click noise(3) influences system application.
The timing example is shown in this figure.
M0040-E-02
-9-
2000/11
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