AK4352 Datasheet, PDF (7/13 Pages) Asahi Kasei Microsystems – 2V & LOW POWER MULTI-BIT DAC

ASAHI KASEI
[AK4352]
OPERATION OVERVIEW
n System Clock
The external clocks which are required to operate the AK4352 are MCLK (256fs/384fs) LRCK (fs), BICK (32fs ∼).
The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The frequency of MCLK
is determined by the sampling rate (LRCK) and CKS pin. Setting CKS= “L” selects an MCLK frequency of 256fs
while setting CKS= “H” selects 384fs. When the 384fs is selected, the internal master clock becomes
256fs(=384fs*2/3). Table 1 illustrates standard audio word rates and corresponding frequencies used in the AK4352.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4352 is in normal operation
mode ( PD = “H”). If these clocks are not provided, the AK4352 may draw excess current because the device utilizes
dynamic refreshed logic internally. If the external clocks are not present, the AK4352 should be in the power-down
mode( PD = “L”).
As the AK4352 includes the phase detection circuit for LRCK, the AK4352 adjusts the phase of LRCK automatically
when the synchronization is out of phase by changing the clock frequencies. Therefore, the reset is only needed for
power-up.
LRCK (fs)
32.0kHz
44.1kHz
48.0kHz
MCLK
CKS= “L”: 256fs CKS= “H”: 384fs
8.1920MHz
12.2880MHz
11.2896MHz
16.9344MHz
12.2880MHz
18.4320MHz
Table 1. Examples of System Clock
BICK (64fs)
2.0480MHz
2.8224MHz
3.0720MHz
256fs or 384fs
MCLK
2/3
H
CKS
L
Figure 1. Internal Clock Circuit
256fs
M0040-E-02
-7-
2000/11