AK4352 Datasheet, PDF (6/13 Pages) Asahi Kasei Microsystems – 2V & LOW POWER MULTI-BIT DAC

ASAHI KASEI
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=1.8 ∼ 3.6V)
Parameter
Master Clock Timing
256fs:
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
Symbol
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
min
2.048
28
28
3.072
23
23
typ
11.2896
16.9344
LRCK Frequency
Serial Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
(Note 8)
fs
8
44.1
tBCK
tBCKL
tBCKH
312.5
100
100
BICK rising to LRCK Edge (Note 9) tBLR
50
LRCK Edge to BICK rising (Note 9) tLRB
50
SDATA Hold Time
tSDH
50
SDATA Setup Time
tSDS
50
Reset Timing
PD Pulse Width
(Note 10) _tRST
300
Note 8. Refer to the operating overview section “Audio Data Interface”.
Note 9. BICK rising edge must not occur at the same time as LRCK edge.
Note 10. The AK4352 can be reset by bringing PD = “L” to “H” only upon power up.
[AK4352]
max
Units
12.8
MHz
ns
ns
19.2
MHz
ns
ns
50
kHz
ns
ns
ns
ns
ns
ns
ns
ns
n Timing Diagram
LRCK
BICK
SDATA
PD
M0040-E-02
tBLR
tLRB
tBCKH
tSDS
LSB
tSDH
Audio Data Input Timing
tRST
Reset Timing
-6-
tBCKL
50%
VDD
50%
VDD
50%
VDD
25%VDD
2000/11