AK4352 Datasheet, PDF (10/13 Pages) Asahi Kasei Microsystems – 2V & LOW POWER MULTI-BIT DAC

ASAHI KASEI
[AK4352]
n System Reset
The AK4352 should be reset once by bringing PD = “L” upon power-up. The internal timing starts clocking by
LRCK “↑” upon exiting reset.
SYSTEM DESIGN
Figure 6 shows the system connection diagram. An evaluation board [AKD4352] is available in order to allow an easy
study on the layout of a surrounding circuit.
External
Clock
Reset
Audio
Data
Processor
Mode
Setting
System Ground
1 MCLK
CKS 16
2 PD
3 BICK
4 SDATA
VCML 15
AK4352 ^{AOUTL 14}
AOUTR 13
+
10µ
+
5 LRCK
6 DIF0
VCMR 12
Top View
VREF 11
10µ ⁺
+
7 DIF1
8 DEM
VDD 10
VSS 9
+
0.1µ 10µ
Analog Ground
Figure 6. Typical Connection Diagram
Lch
Out
Rch
Out
Analog 2V
Notes:
- LRCK = fs, BICK ≥ 32fs or 36fs, MCLK = 256fs/384fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
M0040-E-02
- 10 -
2000/11