AKD4552-A Datasheet, PDF (8/33 Pages) Asahi Kasei Microsystems – 24bit A/D and D/A converter,

ASAHI KASEI
[AKD4552-A]
(6) All interface signals including master clock are fed externally.
Under the following set-up, all external signals needed for the AK4552 to operate could be fed through PORT3
(ROM). In case of interfacing external sources to D/A converter, JP6 (SDTI) should be open. And in case of
using A/D data to externally, JP6 (SDTI) is set ADC side. When JP6 (SDTI) is open, the A/D data can be output
from the SDTO pin of PORT3 (ROM) at the same time if JP5 (SDTO) is short.
JP3
LRCK
JP4
BCLK
JP6
SDTI
JP8
JP13
XTE
EXT
ADC DIR ADC DIR ADC DIR
• Clock example
6-1) Normal speed, Double speed, 4 times speed of ADC and DAC
Do not use X2.
JP2
MCKO
M1 M2
JP7
SPEED
X4
X2
X1
JP9
MCLK
X1
X2
JP10
BCFS
X1
X4
JP11
CLK
JP12
LRFS
DIR
EXT X1
X4
XTL
SW2
MODE
12345
H
LLLL
„ DIP switch set up
Upper-side is “H” and lower-side is “L”.
[SW2] (MODE) : Sets the de-emphasis filter of AK4552 and clock mode of U4 (AK4112B).
No. Pin Name
Mode
1
DEM0
2
DEM1
See Table 2.
3
OCKS0
4
OCKS1
See Table 3.
5
CM0
L : X’tal mode, H : PLL mode
Table 1. Set up SW2
DEM1
DEM0
Mode
L
L
44.1kHz
L
H
OFF
default
H
L
48kHz
H
H
32kHz
Table 2. Set up of DEM0/1 of AK4552
No.
OCKS1
OCKS0
MCKO1
MCKO2
fs (kHz)
0
L
L
256fs
256fs
32, 44.1, 48, 96
1
H
L
512fs
128fs
32, 44.1, 48
Table 3. Set up of OCKS0/1 for AK4112B
<KM080600>
-8-
2005/10