AKD4552-A Datasheet, PDF (6/33 Pages) Asahi Kasei Microsystems – 24bit A/D and D/A converter,

ASAHI KASEI
[AKD4552-A]
3-3) Double speed (MCLK=256fs)
Master clock frequency example of X1 : X1 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2
MCKO
M1 M2
JP7
SPEED
X4
X2
X1
JP9
MCLK
X1
X2
JP10
BCFS
X1
X4
JP11
CLK
JP12
LRFS
DIR
EXT X1
X4
XTL
SW2
MODE
12345
H
H
LLL
(4) Evaluation of D/A using A/D converted data
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s A/D evaluation boards with PORT3 (ROM). Nothing should be connected to PORT1 (DIR). In case of
using external clock through a BNC connector (J5), select EXT on JP11 (CLK) and short JP8 (XTE) and open
JP13 (EXT). This mode corresponds to normal speed only.
JP3
LRCK
JP4
BCLK
JP6
SDTI
JP8
JP13
XTE
EXT
ADC DIR ADC DIR ADC DIR
• Clock example
4-1) Normal speed of DAC (MCLK=256fs)
Master clock frequency example of X2 : X2 = 8.192MHz, 11.2896MHz, 12.288MHz
JP2
MCKO
M1 M2
JP7
SPEED
X4
X2
X1
JP9
MCLK
X1
X2
JP10
BCFS
X1
X4
JP11
CLK
JP12
LRFS
DIR
EXT X1
X4
XTL
SW2
MODE
12345
H
LLLL
4-2) Normal speed of DAC (MCLK=512fs)
Master clock frequency example of X2 : X2 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2
MCKO
M1 M2
JP7
SPEED
X4
X2
X1
JP9
MCLK
X1
X2
JP10
BCFS
X1
X4
JP11
CLK
JP12
LRFS
DIR
EXT X1
X4
XTL
SW2
MODE
12345
H
LLLL
<KM080600>
-6-
2005/10