AKD4552-A Datasheet, PDF (4/33 Pages) Asahi Kasei Microsystems – 24bit A/D and D/A converter,

ASAHI KASEI
[AKD4552-A]
(2) Evaluation of D/A using DIR (Optical Link)
PORT1 (DIR) is used. DIR generates MCLK, BCLK, LRCK and SDATA from the received data through
optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to
PORT3 (ROM). Set up “H” (AK4112B : PLL mode) for SW2-5 (CM0).
JP3
LRCK
JP4
BCLK
JP6
SDTI
JP8
JP13
XTE
EXT
ADC DIR ADC DIR ADC DIR
• Clock example
2-1) Normal speed of DAC (MCLK=256fs)
Input fs example for PORT1 : fs = 32kHz, 44.1kHz, 48kHz
JP2
MCKO
M1 M2
JP7
SPEED
X4
X2
X1
JP9
MCLK
X1
X2
JP10
BCFS
X1
X4
JP11
CLK
JP12
LRFS
DIR
EXT X1
X4
XTL
SW2
MODE
12345
H
LLLL
2-2) Normal speed of DAC (MCLK=512fs)
Input fs example for PORT1 : fs = 32kHz, 44.1kHz, 48kHz
JP2
MCKO
M1 M2
JP7
SPEED
X4
X2
X1
JP9
MCLK
X1
X2
JP10
BCFS
X1
X4
JP11
CLK
JP12
LRFS
DIR
EXT X1
X4
XTL
SW2
MODE
12345
H
H
LL
L
2-3) Double speed of DAC (MCLK=256fs)
Input fs example for PORT1 : fs = 64kHz, 88.2kHz, 96kHz
JP2
MCKO
M1 M2
JP7
SPEED
X4
X2
X1
JP9
MCLK
X1
X2
JP10
BCFS
X1
X4
JP11
CLK
JP12
LRFS
DIR
EXT X1
X4
XTL
SW2
MODE
12345
H
LLLL
<KM080600>
-4-
2005/10