AKD4552-A Datasheet, PDF (5/33 Pages) Asahi Kasei Microsystems – 24bit A/D and D/A converter,

ASAHI KASEI
[AKD4552-A]
2-4) 1/2 decimation of DAC (MCLK=128fs)
Input fs example for PORT1 : fs = 64kHz, 88.2kHz, 96kHz
JP2
MCKO
M1 M2
JP7
SPEED
X4
X2
X1
JP9
MCLK
X1
X2
JP10
BCFS
X1
X4
JP11
CLK
JP12
LRFS
DIR
EXT X1
X4
XTL
SW2
MODE
12345
H
H
L
LL
(3) Evaluation of loopback mode (default)
Using U4 (AK4112B) and X1 (X’tal). Nothing should be connected to PORT1 (DIR), PORT3 (ROM). Set up
“H” (AK4112B : X’tal mode) for SW2-5 (CM0).
JP3
LRCK
JP4
BCLK
JP6
SDTI
JP8
JP13
XTE
EXT
ADC DIR ADC DIR ADC DIR
• Clock example
3-1) Normal speed (MCLK=256fs)
Master clock frequency example of X1 : X1 = 8.192MHz, 11.2896MHz, 12.288MHz
JP2
MCKO
M1 M2
JP7
SPEED
X4
X2
X1
JP9
MCLK
X1
X2
JP10
BCFS
X1
X4
JP11
CLK
JP12
LRFS
DIR
EXT X1
X4
XTL
SW2
MODE
12345
H
H
LLL
3-2) Normal speed (MCLK=512fs)
Master clock frequency example of X1 : X1 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2
MCKO
M1 M2
JP7
SPEED
X4
X2
X1
JP9
MCLK
X1
X2
JP10
BCFS
X1
X4
JP11
CLK
JP12
LRFS
DIR
EXT X1
X4
XTL
SW2
MODE
12345
H
HH
LL
<KM080600>
-5-
2005/10