AK8451 Datasheet, PDF (8/42 Pages) Asahi Kasei Microsystems – 1 channel-input 16 bit 6MSPS ADC

ASAHI KASEI
[AK8451]
„ AFE block, Analog characteristics
(AVDD=3.3V, DRVDD=3.3V, MCLK=40MHz,Single Edge Mode, Ta=25°C,
Item
VCOM voltage
VRP voltage
VRN voltage
VREF voltage
at current sink error
at current source error
Maximum signal input level
Absolute gain
Sampling rate
Input reference level
VCLP input resistence
Input signal range
Clamp level (VCLP voltage)
Clamp resister
Min. Typ. Max.
Reference voltage
1.4
1.5
1.6
1.9
2.0
2.1
0.9
1.0
1.1
1.0
1.1
1.2
+0.1
-0.1
Analog input
1.98
–0.7
0
0.7
–1.50 –0.60 0.30
1
6
0
1.1
1.5
10
60
0
AVDD
1.98 2.08 2.18
7
10
Unit
unless otherwise specified)
Remarks
V
V
V
V Band Gap error
V @ I=10mA ( diff. @I=0mA)
V @ I=-10mA( diff. @I=0mA)
Vp-p
dB
dB
MSPS
V
kΩ
V
V
kΩ
At DC mode (Note 1)
At CDS mode (Note 1)
At DC mode
At DC mode
At DC mode （Note 2）
At CDS mode
At CDS mode
CDS advantage
-40
dB (note 11)
Black level correction DAC
Resolution
8
bit (Note 3)
Correctable range
±215 ±240 ±265 mV (Note 4)
Internal offset voltage
–50
50
mV (Note 5)
PGA(Programmable Gain Amp.) circuit
Resolution
6
bit
Min. gain
0
dB
Max. gain
13.3 13.9 14.5 dB (Note 7)
Video ADC
Resolution
16
bit
DNL
–16
+16 LSB
INL
-96
±32
+96 LSB
Noise
Output noise
6
LSBrms PGA min.
16
LSBrms PGA max.
Power Consumption
Analog part
31.5.
47
mA At DC mode (Note 7)
power dissipations
35.5
52
mA At CDS mode (Note 7)
0.1
mA At power down (Note 8)
Digital output driver power
3
6
mA (Note 9)
dissipation
(Note 1) 0dB is defined at the gain where ADC output reaches its full-scale when 1.98Vpp signal
is input with PGA setting at 00h.
(Note 2) At 2 bit bus mode.
(Note ３) CISIN0 input signal must be in this range which is referenced to AVSS.
(Note 4) Monotonicity guaranteed.
(Note 5) ±50 mV of the total correctable range is used for internal offset adjustment.
MS0937-E-01
8
2011/04