AK8451 Datasheet, PDF (18/42 Pages) Asahi Kasei Microsystems – 1 channel-input 16 bit 6MSPS ADC

ASAHI KASEI
[AK8451]
Bit. 2^nd~4^th Bits are assigned for Register Address where the 2^nd Bit is MSB and the 4^th Bit is
LSB. 9^th~ 16^th Bits are assigned for Data where the 9^th Bit is MSB and the 16^th Bit is LSB.
16 and more rising edges of SDCLK are required while SDENB is low, from the time to fall to
the time to rise. When it is less than 16 rises, registers will not be written properly.
If it is more than 16 rises while SDENB is low, from falling to rising, the last 16 edges become
effective. There is a possibility that an erroneous data will be written into registers if noises
occur on D0 Output / SDCLK input pin and D1 Output / SDATA input pin when these pins are at
High-Z conditions. To avoid this, resistors should be connected between D0 / SDCLK pin, D1 /
SDATA pin and AVSS respectively to pull-down these pins.
SDENB
D0
SDCLK
D1
SDATA
High-Z
High-Z
0 A2 A1 A0 0 0 0 0 B7 B6 B5 B4 B3 B2 B1 B0
Register Write
00
MS0937-E-01
18
2011/04