AK8451 Datasheet, PDF (11/42 Pages) Asahi Kasei Microsystems – 1 channel-input 16 bit 6MSPS ADC

ASAHI KASEI
[AK8451]
■ AFE block, Switching characteristics
(AVDD=3.135~3.465V, DRVDD=3.0~3.6V, Ta=0∼70°C , unless otherwise specified)
No.
Item
pin
min. typ. max. unit
Condition
1 MCLK cycle time (T) MCLK
41.6
250 ns mode 1(note 2)
20.8
125
mode 2(note 2)
41.6
250
mode 3(note 2)
2 MCLK H / L width
MCLK
20.8
ns mode 1(note 2)
10.4
mode 2(note 2)
20.8
mode 3(note 2)
3 TSMP setup time
TSMP
5
ns Note 1
(referenced to MCLK↑)
4 TSMP hold time
TSMP
5
ns Note 1
(referenced to MCLK↑)
5 Aperture delay
CISIN
2
ns Data level
(referenced to MCLK↑)
6 Aperture delay
CISIN
2
ns Reference level
(referenced to MCLK↑)
7 TSMP cycle
TSMP
4T
mode 1(note 2)
(MCLK period-unit )
8T
mode 2(note 2)
4T
mode 3(note 2)
8 Data output delay D0,
At load: 20pF
(referenced to MCLK↑) D1,D2,D3
Drivability
2
25 ns
: normal mode
2
20 ns
: x2 mode
9 Pipeline delay
D0,
6
At 4bit bus
(SMP period-unit ) D1,D2,D3
5
At 2bit bus
10 Reset pulse width
RESETB
50
ns
Note 1) Number of MCLK rising edges during TSMP = H duration is allowed to be 1 to 3 times in
Single Edge, 2bit bus Mode operation, and only a single edge is allowed in the other mode
operation.
Note 2) mode 1 ~ mode 3 explanation
mode 1 : single edge/ 4bit bus mode
mode 2 : single edge/ 2bit bus mode
mode 3 : double edge/ 2bit bus mode
MS0937-E-01
11
2011/04