AK8181G Datasheet, PDF (8/10 Pages) Asahi Kasei Microsystems – 3.3V LVDS 1:4 Clock Fanout Buffer

AK8181G
Function Table
The following table shows the inputs/outputs clock state configured through the control pins.
Table 1: Control Input Function Table
Inputs
OE
CLK_EN CLK_SEL Selected Source
1
0
0 (Open)
CLK1
1
0
1
CLK2
1
1 (Open)
0 (Open)
CLK1
1
1 (Open)
1
CLK2
0
Don’t care Don’t care
---
Outputs
Q0:Q3
Q0n:Q3n
Disabled: Low
Disabled: High
Disabled: Low
Disabled: High
Enabled
Enabled
Enabled
Enabled
Hi-Z
Hi-Z
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 12. In the active mode, the state of the outputs are a function of the CLK1 and CLK2 inputs
as described in Table 2.
Figure 12 CLK_EN Timing Diagram
Table 2: Clock Input Function Table
Inputs
CLK1/2
Q0 : Q3
Outputs
Q0n : Q3n
0
Low
High
1
High
Low
Feb-2013
draft-E-01
-8-