AK8181G Datasheet, PDF (2/10 Pages) Asahi Kasei Microsystems – 3.3V LVDS 1:4 Clock Fanout Buffer

AK8181G
Pin Descriptions
Package: 20-Pin TSSOP(Top View)
Pin No.
1
2
3
4
5
6
7
8
9
10
11, 12
13
14, 15
16, 17
18
19, 20
Pin Name
VSS
CLK_EN
CLK_SEL
CLK1
NC
CLK2
NC
OE
VSS
VDD
Q3n, Q3
VSS
Q2n, Q2
Q1n, Q1
VDD
Q0n, Q0
Pin
Type
PWR
IN
IN
IN
--
IN
--
IN
PWR
PWR
OUT
PWR
OUT
OUT
PWR
OUT
Pullup
down
---
Pull up
Pull down
Pull down
---
Pull down
---
Pull up
---
---
---
---
---
---
---
---
Description
Negative power supply
Synchronizing clock output enable (LVCMOS/LVTTL)
Pin is connected to VDD by internal resistor. (typ. 51kΩ
High (Open): clock outputs follow clock input.
Low: Q outputs are forced low, Qn outputs are forced high.
CLK Select Input (LVCMOS/LVTTL)
Pin is connected to VSS by internal resistor. (typ. 51kΩ
High: selects CLK2 input
Low (Open): selects CLK1 input
Single-ended clock input
Pin is connected to VSS by internal resistor. (typ. 51kΩ
No connect
Single-ended clock input
Pin is connected to VSS by internal resistor. (typ. 51kΩ
No connect
Output enable. Controls enabling and disabling of outputs Q0,
Q0n through Q3, Q3n.
Pin is connected to VDD by internal resistor. (typ. 51kΩ
Negative power supply
Positive power supply
Differential clock output (LVDS)
Negative power supply
Differential clock output (LVDS)
Differential clock output (LVDS)
Positive power supply
Differential clock output (LVDS)
Ordering Information
Part Number
Marking
AK8181G
AK8181G
Shipping
Packaging
Tape and Reel
Package
20-pin TSSOP
Temperature
Range
-40 to 85 °C
Feb-2013
draft-E-01
-2-