AK8181G Datasheet, PDF (1/10 Pages) Asahi Kasei Microsystems – 3.3V LVDS 1:4 Clock Fanout Buffer

AK8181G
3.3V LVDS 1:4
Preliminary Clock Fanout Buffer
AK8181G
Features
Four differential 3.3V LVDS outputs
Selectable two LVCMOS/LVTTL clock inputs
Clock output frequency up to 650MHz
Translates LVCMOS/LVTTL input signals to
LVDS levels
Output skew : 30ps (maximum)
Part-to-part skew : 500ps (maximum)
Propagation delay : 2.2ns (maximum)
Additive phase jitter(RMS): 0.1ps (typical)
Operating Temperature Range: -40 to +85℃
Package: 20-pin TSSOP (Pb free)
Pin compatible with ICS8545I
Description
The AK8181G is a member of AKM’s LVDS clock
fanout buffer family designed for telecom,
networking and computer applications, requiring a
range of clocks with high performance and low
skew. The AK8181G distributes 4 buffered clocks.
AK8181G are derived from AKM’s long-term-
experienced clock device technology, and enable
clock output to perform low skew. The AK8181G is
available in a 20-pin TSSOP package.
Block Diagram
draft-E-01
-1-
Feb-2013