AK8181G Datasheet, PDF (5/10 Pages) Asahi Kasei Microsystems – 3.3V LVDS 1:4 Clock Fanout Buffer

AK8181G
AC Characteristics
All specifications at VDD=3.3V5%, VSS=0V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN TYP MAX Unit
Output Frequency
fOUT
650 MHz
Propagation Delay ⁽¹⁾
Output Skew ^{(2) (3)}
Part-to-Part Skew ^{(3) (4)}
Buffer Additive Jitter, RMS ⁽⁵⁾
Output Rise/Fall Time ⁽⁵⁾
tPD
tsk(O)
tskPP
tjit
tr, tf
0.7
156.25MHz (12kHz – 20MHz)
20% to 80% @50MHz
100
2.2 ns
30 ps
500 ps
0.1
ps
500 ps
Output Duty Cycle
DCOUT
45
55 %
All parameters measured at f ≤ 650MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
(1) Measured from VDD/2 of the input to the differential output crossing point.
(2) Defined as skew between outputs at the same supply voltage and with equal load conditions.
(3) This parameter is defined in accordance with JEDEC Standard 65.
(4) Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
(5) Design value.
draft-E-01
-5-
Feb-2013