AK4351 Datasheet, PDF (8/14 Pages) Asahi Kasei Microsystems – 18 BIT ADVANCED MULTI BIT 2CH DAC

ASAHI KASEI
[AK4351]
OPERATION OVERVIEW
n System Clock
The external clocks, which are required to operate the AK4351, are MCLK, LRCK and BICK. The master clock
(MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital
interpolation filter and the delta-sigma modulator. The frequency of MCLK is determined by the sampling rate (LRCK)
and CKS pin. Table 1 illustrates corresponding clock frequencies. When the 384fs is selected, the internal master clock
becomes 256fs(=384fs*2/3).
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4351 is in normal operation
mode ( PD = ”H”). If these clocks are not provided, the AK4351 may draw excess current because the device utilizes
dynamic refreshed logic internally. The AK4351 should be reset by PD = ”L” after threse clocks are provided. If the
external clocks are not present, the AK4351 should be in the power-down mode( PD = ”L”). After exiting reset at
power-up etc., the AK4351 is in power-down mode until MCLK and LRCK are input. When those clocks are changed
during the operation, please reset the AK4351 at once by PD = ”L”.
Clock
LRCK (fs)
BICK
MCLK
CKS = “L”
CKS = “H”
frequency
8k ~ 50kHz
~ 64fs
256fs
384fs
Table 1. System Clocks
n Audio Serial Interface Format
Data is shifted in via the SDATA pin using BICK and LRCK inputs. The DIF0-1 pins as shown in Table 2 can select
four serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge
of BICK. Mode 2 can be used for 16MSB justified formats by zeroing the unused LSBs.
DIF1
0
0
1
1
DIF0
0
1
0
1
Mode
BICK
0: 16bit LSB Justified
³32fs
1: 18bit LSB Justified
³36fs
2: 18bit MSB Justified
3: I²S Compatible
³36fs
³36fs or 32fs
Table 2. Serial Data Modes
Figure
Figure 1
Figure 1
Figure 2
Figure 3
LRCK
Lch
Rch
BICK
SDATA
Mode 0
SDATA
Mode 1
Don’t care
15 14
15:MSB, 0:LSB (@16bit Data)
Don’t care
17 16 15 14
17:MSB, 0:LSB (@18bit Data)
0 Don’t care
0 Don’t care
15 14
0
17 16 15 14
0
Figure 1. Mode 0,1 Timing
M0022-E-04
-8-
1999/12