AK4351 Datasheet, PDF (2/14 Pages) Asahi Kasei Microsystems – 18 BIT ADVANCED MULTI BIT 2CH DAC

ASAHI KASEI
[AK4351]
n Ordering Guide
AK4351VT
AKD4351
n Pin Layout
DIF1
LRCK
BICK
SDATA
PD
MCLK
DEM
CKS
-40 ~ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4351
1
16
DIF0
2
15
VSS
3
14
VDD
4
Top
13
VREF
View
5
12
VCOM
6
11
AOUTL
7
10
AOUTR
8
9
TST
PIN/FUNCTION
No. Pin Name
I/O Function
1 DIF1
I Digital Input Format Pin
(Internal Pull-down pin)
2 LRCK
I L/R Clock Pin
3 BICK
I Audio Serial Data Clock Pin
4 SDATA
I Audio Serial Data Input Pin
5
PD
I Power-Down Mode Pin
When at “L”, the AK4351 is in power-down mode and is held in reset.
The AK4351 should always be reset upon power-up.
6 MCLK
I Master Clock Input Pin
An external TTL clock should be input on this pin.
7 DEM
I De-emphasis Enable Pin
When at “H”, de-emphasis of fs=44.1kHz is enabled.
8 CKS
I Master Clock Select Pin
(Internal Pull-down pin)
“L”: MCLK=256fs, “H”: MCLK=384fs
9 TST
O Test Pin
Must be left floating.
10 AOUTR
O Rch Analog Output Pin
11 AOUTL
O Lch Analog Output Pin
12 VCOM
O Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with
a 10µF electrolytic cap.
13 VREF
I Voltage Reference Input Pin
The differential Voltage between this pin and VSS set the analog output range.
Normally connected to VDD.
14 VDD
- Power Supply Pin
15 VSS
- Ground Pin
16 DIF0
I Digital Input Format Pin
(Internal Pull-down pin)
Note: All input pins except pull-down pins should not be left floating.
M0022-E-04
-2-
1999/12