AK4351 Datasheet, PDF (11/14 Pages) Asahi Kasei Microsystems – 18 BIT ADVANCED MULTI BIT 2CH DAC

ASAHI KASEI
[AK4351]
SYSTEM DESIGN
Figure 5 shows the system connection diagram. An evaluation board [AKD4351] is available in order to allow an easy
study on the layout of a surrounding circuit.
Analog 5V
Decoder
Reset
External
Clock
Mode
Setting
System Ground
1 DIF1
2 LRCK
DIF0 16
VSS 15
0.1u 10u
3 BICK
AK4351 ^{VDD 14}
+
4 SDATA
VREF 13
5 ^PD
VCOM 12
10u
+
6 MCLK
7 DEM
Top View
AOUTL 11
AOUTR 10
+
Lch
10u
220
Out
27k
8 CKS
TST 9
Analog Ground
+
Rch
10u
220
Out
27k
Figure 5. Typical Connection Diagram
Notes:
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load.
- ALL input pins except internal pull-down pins should not be left floating.
- Decoupling capacitor, especially 0.1µF ceramic capacitor for high frequency should be placed as near to VDD and
VREF pins as possible.
- System ground including DSP/µP should be separated from AK4351’s VSS. Both grounds should be connected by one
point at power supply or regulator on system board.
M0022-E-04
- 11 -
1999/12