AK4351 Datasheet, PDF (6/14 Pages) Asahi Kasei Microsystems – 18 BIT ADVANCED MULTI BIT 2CH DAC

ASAHI KASEI
[AK4351]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=4.5 ~ 5.5V; C_L=20pF)
Parameter
Symbol
min
typ
max
Master Clock Timing 256fs:
fCLK
2.048
11.2896
12.8
Pulse Width Low
tCLKL
28
Pulse Width High
tCLKH
28
384fs:
fCLK
3.072
16.9344
19.2
Pulse Width Low
tCLKL
20
Pulse Width High
tCLKH
20
LRCK Frequency
fs
8
44.1
50
Duty Cycle
Duty
45
55
Serial Interface Timing
BICK Period
tBCK
312.5
BICK Pulse Width Low
tBCKL
100
Pulse Width High
tBCKH
100
BICK rising to LRCK Edge (Note 10) tBLR
50
LRCK Edge to BICK rising (Note 10) tLRB
50
SDATA Hold Time
tSDH
50
SDATA Setup Time
tSDS
50
Reset Timing
PD Pulse Width
(Note 11) tPD
100
Note: 10. BICK rising edge must not occur at the same time as LRCK edge.
11. The AK4351 can be reset by bringing PD = “L”.
When clocks are changed during the operation, please reset the AK4351 at once by PD = ”L”.
Units
MHz
ns
ns
MHz
ns
ns
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
M0022-E-04
-6-
1999/12