AK4351 Datasheet, PDF (12/14 Pages) Asahi Kasei Microsystems – 18 BIT ADVANCED MULTI BIT 2CH DAC

ASAHI KASEI
[AK4351]
1. Grounding and Power Supply Decoupling
VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling capacitor,
especially 0.1mF ceramic capacitor for high frequency should be placed as near to VDD as possible.
2. Voltage Reference
The differential Voltage between VREF and VSS sets the analog output range. VREF pin is normally connected to VDD
with a 0.1µF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10µF parallel with a 0.1µF
ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn
from VCOM pin. ALL signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid
unwanted coupling into the AK4351.
3. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The output signal range is typically
3.45Vpp. AC coupling capacitors of larger than 1µF are recommended. The internal switched-capacitor filter and
continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. Therefore,
any external filters are not required for typical application. The output voltage is a positive full scale for 7FFFH(@16bit)
and a negative full scale for 8000H(@16bit). The ideal output is VCOM voltage for 0000H(@16bit).
DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV.
M0022-E-04
- 12 -
1999/12