AKD4705A-A Datasheet, PDF (7/34 Pages) Asahi Kasei Microsystems – AK4705A Evaluation Board Rev.0

[AKD4705A-A]
3) Feeding all clocks from external
Under the following set-up, all external signals can be fed to the AK4705A through POTR1 (EXT).
The AKM’s evaluation board for ADC can be used.
3)-1. DIP-switch set-up
No. CM0
DIF2
DIF0
1 Don’t care Don’t care Don’t care
Table 4. DIP-switch set-up (DIF1=“L”)
3)-2. Jumper pins set up
JP1
EXT
JP2
MCLK
JP3
BICK
JP4
SDTI
JP5
LRCK
(Open) (Open)
JP6: Don’t care.
(Open)
(Open)
(Open)
Other jumper pins set up
[JP12](VCRRC): Input Jack selection for the VCRRC pin of AK4705A
When the VCRC pin of the AK4705A outputs 0V by setting CIO bit to “1”, the signal can be fed through the
J27 (VCRCOUT) to VCRRC pin.
“I”: The signal is fed through the J18 (VCRRC) to VCRRC pin. (Default)
“I/O”: The signal is fed through the J27 (VCRCOUT) to VCRRC pin.
The CIO bit of AK4705A should be set to “1”.
JP12
I
I/O
JP12
I
I/O
(I)
(Default)
(I/O)
[JP7](GND): Analog ground and digital ground
Open: separated. (Default)
Short: connected. (The jack “DGND” can be open.)
JP7
DGND AGND
(Open)
(Default)
<KM091000>
-7-
2007/09