AKD4705A-A Datasheet, PDF (3/34 Pages) Asahi Kasei Microsystems – AK4705A Evaluation Board Rev.0

[AKD4705A-A]
Evaluation mode
1) S/PDIF mode (Optical Link or BNC: default)
When the CM0 (DIP-switch S1_1 on board) is “L”, the AK4112B (DIR) generates MCLK, BICK, LRCK and
SDATA from the received bit stream through PORT2 (TORX176: optical link) or J2 (BNC). This mode is used
for the evaluation using CD test disk. The PORT1 (EXT) should be open.
1)-1. DIP-switch set-up
No. CM0 DIF2 DIF0 Audio Data Format of AK4112B Notes
1 “L” “L” “L”
16bit LSB justified
1
2 “L” “L” “H”
18bit LSB justified
2
3 “L” “H” “L”
4 “L” “H” “H”
24bit MSB justified
24bit I²S
3
4 (Default)
Table 2. DIP-switch set-up (DIF1=“L”)
Much the data format of the AK4705A via I²C-bus control as following notes.
Note 1. 16bit LSB justified
Set up the DIP-switch as follows.
S1
AK4112B
ON 1 2 3 4 5
OFF
Set up the control registers DIF1/0 of the AK4705A by enclosed software as follows.
Note 2. 18bit LSB justified
Set up the DIP-switch as follows.
S1
AK4112B
ON 1 2 3 4 5
OFF
Set up the control registers DIF1/0 of the AK4705A by enclosed software as follows.
<KM091000>
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2007/09