AKD4705A-A Datasheet, PDF (6/34 Pages) Asahi Kasei Microsystems – AK4705A Evaluation Board Rev.0

[AKD4705A-A]
2) On-board X’tal mode/ Feeding external MCLK via BNC
When the CM0 (DIP-switch S1_1 on board) is “H”, the AK4112B generates MCLK, BICK and LRCK from
on-board X’tal or external clock form J1. SDATA should be fed via PORT1.
2)-1. DIP-switch set-up
No. CM0
DIF2
DIF0
1
“H”
Don’t care Don’t care
Table 3. DIP-switch set-up (DIF1=“L”)
2)-2. Jumper pins set up
2)-2-a. Using on-board X’tal
JP1
JP2
EXT
MCLK
JP3
BICK
JP4
SDTI
JP5
LRCK
(Open) (Short)
JP6: Don’t care.
(Short)
(Open)
2)-2-b. Using external clock via BNC connector J1
JP1
JP2
JP3
EXT
MCLK
BICK
JP4
SDTI
(Short)
JP5
LRCK
(Short) (Short) (Short)
JP6: Don’t care.
Remove the on-board X’tal.
(Open)
(Short)
<KM091000>
-6-
2007/09