AK4545 Datasheet, PDF (7/33 Pages) Asahi Kasei Microsystems – AC97 AUDIO CODEC WITH SRC AND DIT

[ASAHI KASEI]
[AK4545]
Switching Characteristics
Ta=25°C, AVdd=5.0V±5%, DVdd=3.3V±5%, 50pF external load
Parameter
Symbol
Min
Typ
max
Units
Master Clock Frequency Note)
Fmclk
-
24.576
-
MHz
If Crystal is not used.
45
50
55
%
AC link Interface Timing
BIT_CLK frequency
Fbclk
12.288
MHz
BIT_CLK clock Period(Tbclk=1/Fbclk)
Tbclk
-
81.38
ns
BIT_BLK low pulse width
Tclk_low
36
40.7
45
ns
BIT_BLK low pulse width
Tclk_high
36
40.7
45
ns
BIT_CLK rise time
Trise_clk
-
-
6
ns
BIT_CLK fall time
Tfall_clk
-
-
6
ns
SYNC frequency
-
48
-
kHz
SYNC low pulse width
Tsync_low
-
19.5
-
(240 cycle)
µs
(Tbclk)
SYNC high pulse width
Tsync_high
-
1.3
-
µs
(16 cycle)
(Tbclk)
SYNC rise time
Trise_sync
-
-
6
ns
SYNC fall time
Tfall_sync
-
-
6
ns
Setup time(SYNC, SDATA_OUT)
Tsetup
10
-
-
ns
Hold time(SYNC, SDATA_OUT)
Thold
25
-
-
ns
SDATA_IN delay time from BIT_CLK
Tdelay
-
-
15
ns
rising edge
SDATA_IN rise time
Trise_din
-
-
6
ns
SDATA_IN fall time
Tfall_din
-
-
6
ns
SDATA_OUT rise time
Trise_dout
-
-
6
ns
SDATA_OUT fall time
Tfall_dout
-
-
6
ns
Cold Rest (SDATA_OUT=L, SYNC=L)
RESET# active low pulse width
Trst_low
1.0
-
RESET# inactive to BIT_CLK delay
Trst2clk
162.8
-
µs
ns
(2 cycle)
(Tbclk)
Warm Rest Timing
SYNC active low pulse width
Tsync_high
1.0
1.3
-
µs
(16 cycle)
(Tbclk)
SYNC inactive to BIT_CLK delay
Tsync2clk
162.8
ns
(2 cycle)
(Tbclk)
AC-link Low Power Mode Timing
End of Slot 2 to BIT_CLK, SDATA_IN
Ts2_pdwn
-
-
1.0
µs
Low
Activate Test Mode Timing
Setup to trailing edge of RESET#
Tsetup2rst
15.0
-
-
ns
Hold from RESET# rising edge
Thold2rst
100
-
-
ns
Rising edge of RESET# to Hi-Z
Toff
-
-
50
ns
Falling edge of RESET# to “L”
Tlow
-
-
50
ns
Note ) The use of a crystal is recommended. If master clock is supplied from controller (or if a external oscillator is
used), Master Clock should be input to XTAL_IN, meanwhile XTAL_OUT should be open.
MS0058-E-00
-7-
2000/11