AK4545 Datasheet, PDF (16/33 Pages) Asahi Kasei Microsystems – AC97 AUDIO CODEC WITH SRC AND DIT

[ASAHI KASEI]
[AK4545]
b) Slot1
Status Address Port
Audio input frame slot1’s stream echoes the control register index, for historical reference, for the data to be returned in slot2.
(Assuming that slots1 valid bit and slot2 valid bit in the slot0 had been tagged “valid” by the AK4545)
BIT_CLK
SDATA_IN
Slot 0
Bit19 Bit18 Bit17 Bit16 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit19
“0” “1/0” “1/0” “1/0” “1/0” “1/0” “1/0” “1/0” “1/0” “1/0” “0” “0” “0” “0” “0” “0” “0” “0” “0” “0”
Slot 1
Status Address Port
Slot 2
This address shows register index for which data is being returned in the slot2.
This address port is the copy of slot1 of the output frame, and index address input to SDATA_OUT is loop ed back to
the AC’97 controller through SDATA_IN even for non-supported register .
For “On Demand” base data transaction, when the DAC sampling rate is set less than 48kHz, then AK4545 will
request new audio data as required by setting the SLOTREQ bits 11 and 10 in Slot1 to 0 ’s. When no data is required
to support the selected sampling rate, these bits will be 1 ’s. When SLOTREQ bits are asserted as “send data request”
during the current frame on SDATA_IN, AC ’97 digital controller should send data onto the corresponding slot in the
next frame on SDATA_OUT.
If VRA is set “0”, SLOTREQ bits show always “0” and sample rate is forced to 48ksps.
SLOTREQ Bit
19
18 – 12
11
10
9
8
7
6
5
4–0
Description
Reserved ( Set to “0” )
Control Register Index ( Set to “0”s if tagged invalid )
Slot 3 Request : PCM Left channel
“0”: send data request, “1”: do not send
Slot 4 Request : PCM Right channel
“0”: send data request, “1”: do not send
Reserved ( Set to “0” )
Slot 6 Request : AK4545 doesn’t use slot6. ( Set to “0” )
Slot 7 Request : Slot 7 can’t be used at except 48KHz.
Set to “0”.
Slot 8 Request : Slot 8 can’t be used at except 48KHz.
Set to “0”.
Slot 9 Request : AK4545 doesn’t use slot9. ( Set to “0” )
Reserved ( Set to “0” )
c)Slot2: Status Data Port
Status data addressed by command address port of Output Stream is output through SDATA_IN pin.
Bit19:4
Control Register Read Data (the contents of indexed address in the slot 1)
Bit3:0
“0”
Note that the address of Status Data Port data are consistent with Status Address Port data of the slot 1 in the
same frame. If the read operation is issued in the frame N by AC’97 controller, Status Data Port data is output
through SDATA_IN in the frame N+1. Note that data is output in only this frame, only one time and that the
following frames are invalid if the next read operation is not issued.
d)Slot3
PCM Record Left Channel
Record(ADC) data format is MSB first. Data format is 2’s complement. As the resolution of the AK4545 is 18bit,
lower 2 bits are ignored. If ADC block is powered down, slot- 3 valid bit in the slot 0 is invalid ( “0”), and data is
output as all “0”.
Bit19:2
Bit1:0
Audio ADC left channel output
“0”
MS0058-E-00
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