AK4545 Datasheet, PDF (12/33 Pages) Asahi Kasei Microsystems – AC97 AUDIO CODEC WITH SRC AND DIT

[ASAHI KASEI]
[AK4545]
Slot
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
SDATA
TAG Command Command PCM(dac) PCM(dac) All
All SPDIF Out SPDIF Out All
All
All
All
OUT
Address Data
Left
Right
“0”
“0” Channel1 Channel2 “0”
“0”
“0”
“0”
SDATA
TAG
Status Status PCM(adc) PCM(adc) All
All
All
All
All
All
All
All
IN
Address Data
Left
Right
“0”
“0”
”0”
“0”
“0”
“0”
“0”
“0”
Tag Phase
Data Phase
48kHz
AC-link protocol identifies 13slots of data per frame. The frequency of sync is fixed to 48kHz. Only Slot 0, which is
the Tag phase, is 16bits, all other slots are 20bits in length. These slots are explained in later sections.
AC-link Audio Output Frame (SDATA_OUT)
a)Slot 0
SYNC
BIT_CLK
SDATA_OUT
1 BIT_CLK delay
Valid
Frame
Slot1
Bit15 Bit14
“1/0” “1/0”
Slot2 Slot3 Slot4 Slot5
Bit13 Bit12 Bit11 Bit10
“1/0” “1/0” “1/0” “0”
Slot6
Bit9”
“0”
Slot7 Slot8 Slot9
Bit8 Bit7” Bit6”
“1/0” “1/0” “0”
Slot10 Slot11 Slot12 Slot13 Slot14
Bit5” Bit4 Bit3 Bit2 Bit1
“0” “0” “0” “0” “0”
Slot15
Bit0
“0”
Slot 0
Slot 1
The AK4545 checks bit15 (valid frame bit). Note that when the valid frame bit is “1”, at least one bit14-7 (slot 1-8)
must be valid, bit6-0 will be “0”and should be ignored.
If bit15 is “0”, the AK4545 ignores all following information in the frame.
The AK4545 then checks the validity of each bit in the TAG phase (slot 0).
Bit14-11,8,7 are valid bits for slot1-4,7,8.
If each bit is “0”, the AK4545 ignores the slot indicated by “0”. On the other hand, if each bit is “1”, the slot is valid.
A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the
immediately following falling edge of BIT_CLK, the AK4545 samples the assertion of SYNC. This falling edge marks the time when
both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC ’97 controller transitions
SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on a rising edge of
BIT_CLK, and subsequently sampled by the AK4545 on the following falling edge of BIT_CLK. This sequence ensures that data
transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
Data should be sent to the AC’97 codec with MSB first through the SDATA_OUT.
The following table shows the relationship of bit14&13 and the Read/Write operation depending on codec ID
configuration.
Bit 15
Valid Frame
1
1
1
1
Bit14:Slot1Valid Bit Bit13:Slot2ValidBit
Read/Write Operation of
(Command Address)
(Command Data)
AK4545
1
1
Read/Write(Normal Operation)
0
1
Ignore
1
0
Read: Normal Operation
Write: Ignore
0
0
Ignore
AK4545 Addressing: Slot0 Tag Bits
MS0058-E-00
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