AK4393_03 Datasheet, PDF (7/23 Pages) Asahi Kasei Microsystems – Advanced Multi-Bit 96kHz 24-Bit ΔΣ DAC

ASAHI KASEI
[AK4393]
SWITCHING CHARACTERISTICS
(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; C_L = 20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
(Note 17)
Normal Speed: 256fs, Double Speed: 128fs
fCLK
7.7
Pulse Width Low
tCLKL
28
Pulse Width High
tCLKH
28
Normal Speed: 384fs, Double Speed: 192fs
fCLK
11.5
Pulse Width Low
tCLKL
20
Pulse Width High
tCLKH
20
13.824
20.736
MHz
ns
ns
MHz
ns
ns
Normal Speed: 512fs, Double Speed: 256fs
fCLK
15.4
Normal Speed: 768fs, Double Speed: 384fs
fCLK
23.0
Pulse Width Low
tCLKL
7
Pulse Width High
tCLKH
7
LRCK Frequency
(Note 18)
Normal Speed Mode (DFS = “L”)
fsn
30
Double Speed Mode (DFS = “H”)
fsd
60
Duty Cycle
Duty
45
27.648
41.472
MHz
MHz
ns
ns
44.1
54
kHz
88.2
108
kHz
55
%
Serial Interface Timing
BICK Period
tBCK
140
ns
BICK Pulse Width Low
tBCKL
60
ns
Pulse Width High
tBCKH
60
ns
BICK “↑” to LRCK Edge
(Note 19)
tBLR
20
ns
LRCK Edge to BICK “↑”
(Note 19)
tLRB
20
ns
SDATA Hold Time
tSDH
20
ns
SDATA Setup Time
tSDS
20
ns
Control Interface Timing
CCLK Period
tCCK
200
ns
CCLK Pulse Width Low
tCCKL
80
ns
Pulse Width High
tCCKH
80
ns
CDTI Setup Time
tCDS
50
ns
CDTI Hold Time
tCDH
50
ns
CSN High Time
tCSW
150
ns
CSN “↓” to CCLK “↑”
tCSS
50
ns
CCLK “↑” to CSN “↑”
tCSH
50
ns
Reset Timing
PDN Pulse Width
(Note 20)
tPW
150
ns
Notes: 17. For Double Speed mode please see Appendix A for relationship of MCLK and BCLK/LRCK.
18. When the normal and double speed modes are switched, AK4393 should be reset by PDN pin or RSTN bit.
19. BICK rising edge must not occur at the same time as LRCK edge.
20. The AK4393 can be reset by bringing PDN “L” to “H”.
When the states of CKS2-0 or DFS change, the AK4393 should be reset by PDN pin or RSTN bit.
M0039-E-02
-7-
2003/09