AK4393_03 Datasheet, PDF (14/23 Pages) Asahi Kasei Microsystems – Advanced Multi-Bit 96kHz 24-Bit ΔΣ DAC

ASAHI KASEI
[AK4393]
„ System Reset
The AK4393 should be reset once by bringing PDN = “L” upon power-up. The AK4393 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4393 is in the
power-down mode until MCLK and LRCK are input.
„ Power-Down
The AK4393 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z).
Figure 6 shows an example of the system timing at the power-down and power-up.
PDN
Internal
State
D/A In
(Digital)
D/A Out
(Analog)
Clock In
MCLK, LRCK, BICK
Normal Operation
Power-down
“0” data
GD (1)
(3) (2)
(4)
Don’t care
External
MUTE
(5)
Mute ON
Normal Operation
GD (1)
(3)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
Figure 6. Power-down/up sequence example
„ Click Noise from analog output
Click noise occurs from analog output in the following cases.
1) When switching de-emphasis mode by DEM0, DEM1 and DFS pins,
2) When switching serial data mode by DIF0, DIF1 and DIF2 pins,
3) When going and exiting power down mode by PDN pin,
4) When switching normal speed and double speed by DFS pin,
However in case of 1) & 2), If the input data is “0” or the soft mute is enabled (after 1024 LRCK cycles from SMUTE
= “H”), no click noise occur except for switching DFS pin.
M0039-E-02
- 14 -
2003/09