AK4393_03 Datasheet, PDF (17/23 Pages) Asahi Kasei Microsystems – Advanced Multi-Bit 96kHz 24-Bit ΔΣ DAC

ASAHI KASEI
[AK4393]
SYSTEM DESIGN
Figure 8 and 9 show the system connection diagram. An evaluation board (AKD4393) is available which demonstrates
the optimum layout, power supply arrangements and measurement results.
Digital
Supply
Master Clock
Reset & Power down
64fs
24bit Audio Data
fs
Micro-
controller
Digital Ground
10u 0.1u
+
1 DVSS
2 DVDD
3 MCLK
4 PDN
5 BICK
6 SDATA
7 LRCK
8 CSN
9 DFS
10 CCLK
11 CDTI
12 DIF0
13 DIF1
14 DIF2
CKS2 28
CKS1 27
CKS0 26
P/S 25
AK4393 ^{VCOM 24}
AOUTL+ 23
AOUTL- 22
AOUTR+ 21
AOUTR- 20
AVSS 19
0.1u
AVDD 18
VREFH 17
0.1u
VREFL 16
BVSS 15
0.1u
1+0u
Lch
LPF
Rch
LPF
Lch Out
Rch Out
10u
+
Analog
+
Supply 5V
10u
Analog Ground
Figure 8. Typical Connection Diagram (Serial mode)
Notes:
- LRCK = fs, BICK = 64fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of
regulator etc.
- AVSS, BVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins except pull-down/pull-up pins should not be left floating.
M0039-E-02
- 17 -
2003/09