AK4393_03 Datasheet, PDF (23/23 Pages) Asahi Kasei Microsystems – Advanced Multi-Bit 96kHz 24-Bit ΔΣ DAC

ASAHI KASEI
[AK4393]
Appendix A
In Double Speed Mode, the phase relationship between MCLK and LRCK/BICK is limited (Table 7). If the phase
relationship happens during this prohibited period, it is possible to occur the inverse of output channel. The phase
relationship must be set to avoid the prohibited period when the AK4393 operates at Double Speed Mode. The prohibited
period is specified by the combination of digital power supply voltage (DVDD), MCLK frequency and audio data format
(Table 5). When the audio data formats are 16/20/24bit LSB Justified (Mode 0,1,4) and 24bit MSB Justified (Mode 2), the
phase relationship (tLRM: Figure 11) between the rising edge of LRCK and the rising edge of MCLK has the prohibited
period of min to max in Table 7. In case of I²S Compatible (Mode 3), the relationship between the falling edge of BICK
and the rising edge of MCLK has the prohibited period (tBCM: Figure 12)
Sampling
Mode
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Digital Power
Supply, DVDD
3.0 to 5.25V
3.0 to 5.25V
3.0 to 5.25V
3.0 to 5.25V
3.0 to 5.25V
3.0 to 5.25V
4.75 to 5.25V
4.75 to 5.25V
4.75 to 5.25V
4.75 to 5.25V
4.75 to 5.25V
4.75 to 5.25V
MCLK
Frequency
128fs
192fs
256fs
256fs
384fs
384fs
128fs
192fs
256fs
256fs
384fs
384fs
CKS2
0
0
0
1
0
1
0
0
0
1
0
1
Mode Setting
CKS1 CKS0
0
0
1
0
0
1
0
0
1
1
1
0
0
0
1
0
0
1
0
0
1
1
1
0
Table 7. Prohibited Period
Prohibited Period Units
DFS min max
1
0.4
1.7 ns
1
-0.5
0.8
ns
1
-0.7
0.7
ns
1
-0.7
0.7
ns
1
-1.7 -0.3 ns
1
-1.7 -0.3 ns
1
0.8
1.5
ns
1
-0.2
0.5
ns
1
-0.3
0.4
ns
1
-0.3
0.4
ns
1
-1.0 -0.3 ns
1
-1.0 -0.3 ns
LRCK
MCLK
BICK
MCLK
tLRM
Figure 11. 16/20/24bit LSB Justified, 24bit MSB Justified
50%DVDD
50%DVDD
tBCM
Figure 12. I²S Compatible
50%DVDD
50%DVDD
M0039-E-02
- 23 -
2003/09