AK4120 Datasheet, PDF (7/30 Pages) Asahi Kasei Microsystems – Sample Rate Converter with Mixer and Volume

ASAHI KASEI
[AK4120]
SWITCHING CHARACTERISTICS
(Ta=-40∼ 85°C; VDD=2.7~3.6V; C_L=20pF)
Parameter
Symbol
min
Master Clock Input (IMCLK1)
Frequency
fCLK
2.048
Duty Cycle (at FSI > 33kHz)
Duty Cycle (at FSI ≤ 33kHz)
dCLK
40
dCLK
28
Master Clock Input (IMCLK2)
Frequency
fCLK
2.048
Duty Cycle (at FSI > 33kHz)
Duty Cycle (at FSI ≤ 33kHz)
dCLK
40
dCLK
28
Master Clock Input (OMCLK)
Frequency (Note 11)
fCLK
8.192
Duty Cycle (at FSI > 33kHz)
dCLK
40
Duty Cycle (at FSI ≤ 33kHz)
dCLK
28
L/R clock for Input data #1 (ILRCK1)
Frequency
fs
8
Duty Cycle
Duty
48
L/R clock for Input data #2 (ILRCK2)
Frequency
(Note 12)
fs
8
Duty Cycle
Slave Mode
Duty
48
Master Mode
Duty
L/R clock for Output data (OLRCK)
Frequency
(Note 13)
fs
32
Duty Cycle
Slave Mode
Duty
48
Master Mode
Duty
Audio Interface Timing
(Note 14)
Input#1 at Path Mode 0 and 2
Input#2 (Slave Mode) at Path Mode 1
BICK Period
BICK Pulse Width Low
tBCK
325
tBCKL
130
BICK Pulse Width High
LRCK Edge to BICK “↑” (Note 15)
BICK “↑” to LRCK Edge (Note 15)
SDTI1-2, Hold Time from BICK “↑”
SDTI1-2, Setup Time to BICK “↑”
tBCKH
130
tBLR
45
tLRB
45
tSDH
40
tSDS
25
Input#2 (Slave Mode) at Path Mode 0 and 3
BICK Period
tBCK
162
BICK Pulse Width Low
BICK Pulse Width High
LRCK Edge to BICK “↑” (Note 15)
BICK “↑” to LRCK Edge (Note 15)
SDTI2, Hold Time from BICK “↑”
SDTI2, Setup Time to BICK “↑”
tBCKL
65
tBCKH
65
tBLR
45
tLRB
45
tSDH
40
tSDS
25
Output (Slave Mode)
OBICK Period
OBICK Pulse Width Low
OBICK Pulse Width High
tBCK
162
tBCKL
65
tBCKH
65
OLRCK Edge to OBICK “↑”
OBICK “↑” to OLRCK Edge
OLRCK to SDTO (MSB)
OBICK “↓” to SDTO
(Note 15)
(Note 15)
tBLR
45
tLRB
45
tLRS
tBSD
typ
max Units
24.576
60
72
MHz
%
%
24.576
60
72
MHz
%
%
24.576
60
72
MHz
%
%
48
kHz
50
52
%
96
kHz
50
52
%
50
%
96
kHz
50
52
%
50
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
ns
40
ns
MS0134-E-00
-7-
2002/1