AK4120 Datasheet, PDF (16/30 Pages) Asahi Kasei Microsystems – Sample Rate Converter with Mixer and Volume

ASAHI KASEI
[AK4120]
n System Clock
The external clocks required to operate the AK4120 in each mode are shown in Table 3 and Table 4. The Input#1 port
works in slave mode only. The Input#2 and Output ports have both slave and master modes that are selected by the
IMODE2 and OMODE pins. The required external clock shown in Table 2 should be always present whenever the
AK4120 is in a normal operating mode (PDN=”H”).
Path Mode
0
1
2
3
Synchronizing
SRC
Synchronizing
Group A
Group B
SDTI1
Active
SDTI2, SDTO
SDTI2
Active
SDTO
SDTI1, SDTO (Not used)
-
SDTI2, SDTO (Not used)
-
Table 2. Clock Synchronization
(Not used)
-
SDTI1
SDTI2
SDTI1
Path Mode
0
1
2
3
IMCLK1
IMCLK2
Input
(Not used)
(Not used)
Input
Input
(Not used)
(Not used)
(Not used)
Table 3. Master Clock
OMCLK
Input
Input
(Not used)
Input
Path Mode
0
1
2
3
ILRCK1,
IBICK1
Input
(Not used)
Input
(Not used)
ILRCK2, IBICK2
I2MODE = “L” I2MODE = “H”
(Not used)
Output
Input
Output
(Not used)
(Not used)
(Not used)
Output
Table 4. LRCK/BICK
OLRC, OBICK
OMODE= “L” OMODE= “H”
Input
Output
Input
Output
(Not used)
Output
Input
Output
(1) Path Mode 0
IMCLK1 does not need to be synchronized with OMCLK when using Path Mode 1. IMCLK1 should be synchronized
with ILRCK1 (clock phase is not important). STDI2 should be synchronized with OLRCK and OBICK. When the
output is slaved, OMCLK should be synchronized with OLRCK (clock phase is not important). When input#2 is in
slave mode, OLRCK and OBICK are used while ILRCK2 and IBICK2 are not.
(2) Path Mode 1
IMCKL2 does not need to be synchronized with OMCLK. When Input#2 port is in slave mode, IMCLK2 should be
synchronized with ILRCK2 (clock phase is not important). When Output#2 port is in slave mode, OMCLK should be
synchronized with OLRCK (clock phase is not important).
(3) Path Mode 2
IMCLK1 should be synchronized with ILRCK1 (clock phase is not important). SDTO should be synchronized with
ILRCK1 and IBICK1. When the Output is in slave mode, the OLRCK and OBICK pins are not used. In master mode,
ILRCK1 is output through OLRCK and IBICK1 is output through OBICK.
(4) Path Mode 3
OMCLK should be synchronized with OLRCK (clock phase is not important). SDTI2 should be synchronized with
OLRCK and OBICK. When Input#2 is in slave mode, ILRCK2 and IBICK2 pins are not used. In master mode, OLRCK
is output through ILRCK2 and OBICK is output through IBICK2.
MS0134-E-00
- 16 -
2002/1