AK4120 Datasheet, PDF (21/30 Pages) Asahi Kasei Microsystems – Sample Rate Converter with Mixer and Volume

ASAHI KASEI
[AK4120]
2) I²C-bus Control Mode (I2C= “H”)
The AK4120 supports the standard I²C-bus interface (max:100kHz). Then AK4120 cannot support fast-mode I²C (max:
400kHz).
(2)-1. WRITE Operations
Figure 11 shows the data transfer sequence in I²C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 17). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction
bit (R/WN). The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and
CAD0 (device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1
pin and CAD0 pin) set them (Figure 12). If the slave address matches that of the AK4120, the AK4120 generates the
acknowledge and the operation is executed. The master must generate an acknowledge-related clock pulse and release
the SDA line (HIGH) during the acknowledge clock pulse (Figure 18). A “1” for R/WN bit indicates that the read
operation is to be executed. A “0” indicates that the write operation is to be executed.
The second byte is the control register address of the AK4120. The format is MSB first, and three most significant bits
are fixed to zero (Figure 13). Subsequent bytes contain control data. The format is MSB first, 8-bits (Figure 14). The
AK4120 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP
condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP
condition (Figure 17).
The AK4120 is capable of more than one byte write operation per sequence. After receipt of the third byte, the AK4120
generates an acknowledge, and awaits the next data. The master can transmit multiple bytes rather than terminating the
write cycle after the first data byte is transferred. After the receipt of each data, the internal 5-bit address counter is
incremented by one, and the next data is taken into next address automatically. If the address exceeds 06H prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. (If an
address greater than 07H is set, this function will not work properly.)
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 19) except for START and STOP conditions.
SDA
S
T
S
A
R/WN= “0”
T
R
O
T
P
S
Slave
Address
Sub
Address(n)
Data(n)
Data(n+1)
Data(n+x) P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 11. Data transfer sequence at the I²C-bus mode
0
0
1
0
0 CAD1 CAD0 R/WN
(Those CAD1/0 should match with CAD1/0 pins)
Figure 12. The first byte
0
0
0
A4
A3
A2
A1
A0
Figure 13. The second byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 14. Byte structure after the second byte
MS0134-E-00
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