AKD4563A Datasheet, PDF (6/26 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4563A

ASAHI KASEI
[AKD4563A]
5) Evaluation of A/D using D/A converted data.
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s D/A evaluation boards with PORT3. Nothing should be connected to PORT4. When SDTO0 is
supplied from PORT1, JP8 (SD0/1) selects SD0 side. When SDTO1 is supplied from PORT1, JP8 (SD0/1)
selects SD1 side.
JP3
X_BCLK
JP4
LRCK
JP5
BCLK
JP9
SDTI
JP10
DIR
JP11
CLK
JP12
XTE
32fs 64fs ADC DIR ADC DIR ADC DIR VD GND
6) Evaluation of A/D using DIT. (Optical link)
PORT1 (DIT) is used. DIT generates audio bi-phase signal from received data and which is output through
optical connector (TOTX176). It is possible to connect AKM’s D/A converter evaluation boards on the
digital-amplifier which equips DIR input. Nothing should be connected PORT3 and PORT4. In case of
using external clock through a BNC connector (J1), select EXT on JP11 (CLK) and short JP12 (XTE).
When SDTO0 is supplied from PORT1, JP8 (SD0/1) selects SD0 side. When SDTO1 is supplied from
PORT1, JP8 (SD0/1) selects SD1 side.
JP3
X_BCLK
JP4
LRCK
JP5
BCLK
JP9
SDTI
JP10
DIR
JP11
CLK
JP12
XTE
32fs 64fs ADC DIR ADC DIR ADC DIR VD GND
7) All interfacing signals (MCLK, BCLK, LRCK) are fed from the external circuit through PORT3.
Under the following set up, all external signals needed for the AK4563A to operate could be fed through
PORT3. In case of interfacing external sources to D/A converter, JP7 (SDTO) should be open. And in case
of using A/D data to externally, JP9 (SDTI) is set ADC side. When JP9 (SDTI) is open, the A/D data can be
output from the PORT3, if JP7 (SDTO) is short.
JP3
X_BCLK
JP4
LRCK
JP5
BCLK
JP9
SDTI
JP10
DIR
JP11
CLK
JP12
XTE
32fs 64fs ADC DIR ADC DIR ADC DIR VD GND
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