AKD4373-B Datasheet, PDF (6/34 Pages) Asahi Kasei Microsystems – AK4373 Evaluation Board Rev.1

(2-2) PLL Reference Clock: BICK or LRCK pin
[AKD4373-B]
AK4373
MCKI
MCKO
BICK
LRCK
SDATA
DSP or μP
32fs or 64fs
1fs
BCLK
LRCK
SDTO
Figure 5. PLL Master Mode (PLL Reference Clock : BICK or LRCK pin)
PORT2 (DSP) is used. Nothing should be connected to PORT1 (DIR).
BICK, LRCK and SDATA are supplied from PORT2.
Set up the jumper pins.
JP16
LRCK2
JP17
BICK2
JP11
MCLK
JP12
BICK
JP13
LRCK
JP14
SDTO
<KM091602>
-6-
2008/07