AKD4373-B Datasheet, PDF (4/34 Pages) Asahi Kasei Microsystems – AK4373 Evaluation Board Rev.1

[AKD4373-B]
(1) PLL Master Mode
PORT2 (DSP) is used. Nothing should be connected to PORT1 (DIR). BICK and LRCK are supplied from
PORT2. It is possible to evaluate at various sampling frequencies using built-in the AK4373’s PLL.
AK4373
MCKI
MCKO
BICK
LRCK
SDATA
11.2896MHz,12MHz,12.288MHz
13.5MHz,24MHz,25MHz,27MHz
DSP or μP
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTO
Figure 3. PLL Master Mode
The system clock should be connected to MCLK of PORT2. SDTI of PORT2 should be connected to SDTO of
DSP. The JP16 (LRCK2) and JP17 (BICK2)’s right side should be connected to LRCK and BICK of DSP.
In case of supplying MCKO to DSP, the test pin (MCKO) should be connected to MCLK of DSP.
Set up the jumper pins.
JP16
LRCK2
JP17
BICK2
JP11
MCLK
JP12
BICK
JP13
LRCK
JP14
SDTO
<KM091602>
-4-
2008/07