AKD4373-B Datasheet, PDF (5/34 Pages) Asahi Kasei Microsystems – AK4373 Evaluation Board Rev.1

(2) PLL Slave Mode
(2-1) PLL Reference Clock: MCKI pin
AK4373
MCKI
MCKO
BICK
LRCK
SDATA
11.2896MHz,12MHz,12.288MHz
13.5MHz,24MHz,25MHz,27MHz
DSP or μP
256fs/128fs/64fs/32fs
≥32fs
1fs
MCLK
BCLK
LRCK
SDTO
Figure 4. PLL Master Mode (PLL Reference Clock: MCKI pin)
[AKD4373-B]
PORT2 (DSP) is used. Nothing should be connected to PORT1 (DIR).
MCKO is needed for a synchronous signal of BICK and LRCK.
MCLK, BICK, LRCK and SDATA are supplied from PORT2. The test pin (MCKO) should be connected to
MCLK of DSP.
Set up the jumper pins.
JP16
LRCK2
JP17
BICK2
JP11
MCLK
JP12
BICK
JP13
LRCK
JP14
SDTO
<KM091602>
-5-
2008/07