AK5572 Datasheet, PDF(6/68 Page) Asahi Kasei Microsystems

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AK5572 Datasheet, PDF (6/68 Pages) Asahi Kasei Microsystems – 2-Channel Differential 32-bit ADC

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[AK5572]

No. Pin Name I/O Function

CKS0

31 SDA

I Clock Mode Select Pin

I/O Control Data I/O Pin in I2C Bus Serial Control Mode

CDTI

I Control Data Input Pin in 3-wire Serial Control Mode

CKS1

32 CAD0_I2C

I Clock Mode Select Pin

I Chip Address 0 Pin in I2C Bus Serial Control Mode

CSN

I Chip Select Pin in 3-wire Serial Control Mode

CKS2

33 SCL

I Clock Mode Select Pin

I Control Data Clock Pin in I2C Bus Serial Control Mode

CCLK

I Control Data Clock Pin in 3-wire Serial Control Mode

CKS3

CAD1

I Clock Mode Select Pin

I Chip Address 1 Pin in I2C Bus or 3-wire Serial Control Mode

SLOW

DCKB

I Slow Roll-OFF Digital Filter Select Pin in PCM Mode

I Polarity of DCLK Pin in DSD Mode

PMOD

I Short Delay Digital Filer Select Pin in PCM Mode

I DSD Phase Modulation Mode Select Pin in DSD Mode

DIF0

DSDSEL0

Audio Data Format Select Pin in PCM Mode

âLâ: MSB Justified, âHâ: I2S

I DSD Sampling Rate Control Pin in DSD Mode

DIF1

DSDSEL1

Audio Data Format Select Pin in PCM Mode

âLâ: 24-bit Mode, âHâ: 32-bit Mode

I DSD Sampling Rate Control Pin in DSD Mode

39 TDM0

40 TDM1

PSN

CAD0_SPI

TDM I/F Format Select Pin

* This pin must be fixed to âLâ when using DSD mode.

TDM I/F Format Select Pin

* This pin must be fixed to âLâ when using DSD mode.

Control Mode Select Pin (I2C pin = âHâ)

âLâ:I2C Bus Serial Control Mode, âHâ :Parallel Control Mode

I Chip Address 0 Pin in 3-wire serial control Mode (I2C pin = âLâ)

42 I2C

43 DP

Control Mode Select Pin

I âLâ: 3-wire Serial Control Mode

âHâ: I2C Bus Serial Control Mode or Parallel Control Mode

DSD Mode Enable Pin

âLâ: PCM Mode, âHâ: DSD Mode

44 HPFE

DCKS

I High Pass Filter Enable Pin

âLâ: HPF Disable, âHâ: HPF Enable

I Master Clock Frequency Select at DSD Mode (DSD Only)

45 LDOE

LDO Enable Pin

I âLâ: LDO Disable, âHâ: LDO Enable

This pin is pulled down by 100 kâ¦ internally.

46 ODP

I Optimal Data Placement Mode Enable Pin

47 AIN1P

I Channel 1 Positive Input Pin

48 AIN1N

I Channel 1 Negative Input Pin

Note 1. All digital input pins must not be allowed to float.

Power Down

Status

Hi-z

015016766-E-00

-6-

2015/12

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