AK5572 Datasheet, PDF (42/68 Pages) Asahi Kasei Microsystems – 2-Channel Differential 32-bit ADC

[AK5572]
LRCK (Master)
128 BICK
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
0 31 30 1 0 31 30 1 0
31 30
Data 1 Data 2
32 BICK 32 BICK
Figure 45. Mode 27/31 Timing (TDM128 mode, I²S Compatible)
LRCK (Master)
256 BICK
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22
#4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
TDMIN (I)
23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0
23 22
(#3 SDTO1)
#3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 46. Mode 32/36 Timing (TDM256 mode, MSB Justified, 24-bit)
LRCK (Master)
256 BICK
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23
#4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
TDMIN (I)
(#3 SDTO1)
23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0
#1 Data 1 #1 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 47. Mode 33/37 Timing (TDM256 mode, I²S Compatible, 24-bit)
015016766-E-00
- 42 -
23
2015/12