AK5572 Datasheet, PDF (39/68 Pages) Asahi Kasei Microsystems – 2-Channel Differential 32-bit ADC

[AK5572]
LRCK (Master)
32 BICK
LRCK (Slave)
BICK (32fs)
SDTO1 (O)
0 15 14 9 8 7 6
1 0 15 14 9 8 7 6
1 0 15 14
AIN1 Data
16 BICK
AIN2 Data
16 BICK
Figure 34. Mode 8/16 Timing (Normal mode, OCT/HEX Speed mode, MSB Justified, 16-bit)
LRCK (Master)
32 BICK
LRCK (Slave)
BICK (32fs)
SDTO1 (O)
0 15 14 9 8 7 6
1 0 15 14 9 8 7 6
1 0 15 14
AIN1 Data
16 BICK
AIN2 Data
16 BICK
Figure 35. Mode 9/17 Timing (Normal mode, OCT/HEX Speed mode, I²S Compatible, 16-bit)
LRCK (Master)
48 BICK
LRCK (Slave)
BICK (48fs)
SDTO1 (O)
0 23 22 13 12 11 10 1 0 23 22 13 12 11 10 1 0 23 22
AIN1 Data
24 BICK
AIN2 Data
24 BICK
Figure 36. Mode 10/18 Timing (Normal mode, OCT/HEX Speed mode, MSB Justified, 24-bit)
48 BICK
LRCK (Master)
LRCK (Slave)
BICK (48fs)
SDTO1 (O)
0 23 22 13 12 11 10 1 0 23 22 13 12 11 10 1 0 23 22
AIN1 Data
24 BICK
AIN2 Data
24 BICK
Figure 37. Mode 11/19 Timing (Normal mode, OCT/HEX Speed mode, I²S Compatible, 24-bit)
015016766-E-00
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2015/12