AK4628A Datasheet, PDF (6/41 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC

ASAHI KASEI
[AK4628A]
No. Pin Name
23 LOUT3
24 ROUT3
25 LOUT2
26 ROUT2
27 LOUT1
28 ROUT1
29 TST2
30 NC
31 LIN
32 RIN
33 DZF2
OVF
34 VCOM
35 VREFH
36 AVDD
37 AVSS
38 DZF1
39 MCLK
40 P/S
41 DIF0
CSN
42 DIF1
SCL/CCLK
43 LOOP0
SDA/CDTI
44 TDM0
I/O
Function
O DAC3 Lch Analog Output Pin
O DAC3 Rch Analog Output Pin
O DAC2 Lch Analog Output Pin
O DAC2 Rch Analog Output Pin
O DAC1 Lch Analog Output Pin
O DAC1 Rch Analog Output Pin
I Test pin (Internal pull-down pin)
This pin should be left floating or connected to AVSS.
- No Connect
No internal bonding.
I Lch Analog Input Pin
I Rch Analog Input Pin
O Zero Input Detect 2 Pin
(Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “0”, this pin goes to
“H”. It always is in “L” when P/S is “H”.
O Analog Input Overflow Detect Pin (Note 3)
This pin goes to “H” if the analog input of Lch or Rch overflows.
O Common Voltage Output Pin, AVDD/2
Large external capacitor around 2.2µF is used to reduce power-supply noise.
I Positive Voltage Reference Input Pin, AVDD
- Analog Power Supply Pin, 4.5V∼5.5V
- Analog Ground Pin, 0V
O Zero Input Detect 1 Pin
(Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “0”, this pin goes to
“H”. Output is selected by setting DZFE pin when P/S is “H”.
I Master Clock Input Pin
I Parallel/Serial Select Pin
“L”: Serial control mode, “H”: Parallel control mode
I Audio Data Interface Format 0 Pin in parallel control mode
I Chip Select Pin in 3-wire serial control mode
This pin should be connected to DVDD at I²C bus control mode
I Audio Data Interface Format 1 Pin in parallel control mode
I Control Data Clock Pin in serial control mode
I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I²C Bus)
I Loopback Mode 0 Pin in parallel control mode
Enables digital loop-back from ADC to 4 DACs.
I/O Control Data Input Pin in serial control mode
I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I²C Bus)
I TDM I/F Format Mode Pin (Note 1)
“L”: Normal mode, “H”: TDM mode
Notes: 1. SDOS, SMUTE, DFS0, and TDM0 pins are ORed with register data if P/S = “L”.
2. The group 1 and 2 can be selected by DZFM3-0 bits if P/S = “L” and DZFE = “L”.
3. This pin becomes OVF pin if OVFE bit is set to “1” at serial control mode.
4. All digital input pins except for pull-down should not be left floating.
MS0385-E-00
-6-
2005/02