AK4628A Datasheet, PDF (18/41 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC

ASAHI KASEI
[AK4628A]
„ Audio Serial Interface Format
When TDM= “L”, four modes can be selected by the DIF1-0 as shown in Table 8. In all modes the serial data is
MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI/DAUX are
latched on the rising edge of BICK.
Figures 1∼4 shows the timing at SDOS = “L”. In this case, the SDTO outputs the ADC output data. When SDOS = “H”,
the data input to DAUX is converted to SDTO’s format and output from SDTO. Mode 2, 3, 6, 7, 10, 11 in SDTI input
formats can be used for 16-20bit data by zeroing the unused LSBs.
Mode
0
1
2
3
TDM 1
0
0
0
0
TDM0
0
0
0
0
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I²S
SDTI1-4,
DAUX
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I²S
LRCK
I/O
BICK
I/O
H/L I ≥ 48fs I
H/L I ≥ 48fs I
H/L I ≥ 48fs I ^Default
L/H I ≥ 48fs I
Table 8. Audio data formats (Normal mode)
The audio serial interface format becomes the TDM mode if TDM0 pin is set to “H”. In the TDM256 mode, the serial data
of all DAC (eight channels) is input to the SDTI1 pin. The input data to SDTI2-4 pins are ignored. BICK should be fixed
to 256fs. “H” time and “L” time of LRCK should be 1/256fs at least. Four modes can be selected by the DIF1-0 as shown
in Table 9. In all modes the serial data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge
of BICK and the SDTI1 are latched on the rising edge of BICK. SDOS and LOOP1-0 should be set to “0” at the TDM
mode. TDM128 Mode can be set by TDM1 as show in Table10. In Double Speed Mode, the serial data of DAC (four
channels; L1, R1, L2, R2) is input to the SDTI1 pin. Other four data (L3, R3, L4, R4) are input to the SDTI2. TDM0 pin
and TDM0 register should be set to “H” if TDM256 Mode is selected. TDM0 pin and TDM0 register, TDM1 register
should be set to “H” if Double Speed Mode is selected in TDM128 Mode.
Mode TDM 1 TDM0 DIF1 DIF0 SDTO
SDTI1
4
0
1
0
0
24bit, Left 20bit, Right
justified justified
5
0
1
0
1
24bit, Left 24bit, Right
justified justified
6
0
1
1
0
24bit, Left 24bit, Left
justified justified
7
0
1
1
1
24bit, I²S 24bit, I²S
LRCK
I/O
↑I
BICK
I/O
256fs I
↑ I 256fs I
↑ I 256fs I
↓ I 256fs I
Table 9. Audio data formats (TDM256 mode)
Mode
8
9
10
11
TDM 1
1
1
1
1
TDM0
1
1
1
1
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I²S
SDTI1,
SDTI2
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I²S
LRCK
I/O
↑I
BICK
I/O
128fs I
↑ I 128fs I
↑ I 128fs I
↓ I 128fs I
Table 10. Audio data formats (TDM128 mode)
MS0385-E-00
- 18 -
2005/02