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AK4628A Datasheet, PDF (12/41 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC | |||
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ASAHI KASEI
[AK4628A]
Parameter
Symbol
min
typ
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN âHâ Time
CSN âââ to CCLK âââ
tCSW
150
tCSS
50
CCLK âââ to CSN âââ
Control Interface Timing (I2C Bus mode):
tCSH
50
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
4.7
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
4.0
Clock Low Time
tLOW
4.7
Clock High Time
tHIGH
4.0
Setup Time for Repeated Start Condition
tSU:STA
4.7
SDA Hold Time from SCL Falling
(Note 19)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT 0.25
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
4.0
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Power-down & Reset Timing
PDN Pulse Width
PDN âââ to SDTO valid
(Note 20)
(Note 21)
tPD
tPDV
150
522
Notes: 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
20. The AK4628A can be reset by bringing PDN âLâ to âHâ upon power-up.
21. These cycles are the number of LRCK rising from PDN rising.
22. I2C is a registered trademark of Philips Semiconductors.
max Units
ns
ns
ns
ns
ns
ns
ns
ns
100 kHz
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
1.0
µs
0.3
µs
-
µs
50
ns
ns
1/fs
MS0385-E-00
- 12 -
2005/02
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