AK4628A Datasheet, PDF (16/41 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC

ASAHI KASEI
[AK4628A]
OPERATION OVERVIEW
„ System Clock
The external clocks, which are required to operate the AK4628A, are MCLK, LRCK and BICK. MCLK should be
synchronized with LRCK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting
Mode (ACKS = “0”: Default), the sampling speed is set by DFS0, DFS1 (Table 1). The frequency of MCLK at each
sampling speed is set automatically. (Table 2, 3, 4). In Auto Setting Mode (ACKS = “1”), as MCLK frequency is detected
automatically (Table 5), and the internal master clock becomes the appropriate frequency (Table 6), it is not necessary to
set DFS.
External clocks (MCLK, BICK) should always be present whenever the AK4628A is in normal operation mode (PDN =
“H”). If these clocks are not provided, the AK4628A may draw excess current because the device utilizes dynamic
refreshed logic internally. If the external clocks are not present, the AK4628A should be in the power-down mode (PDN
= “L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4628A is in the power-down mode
until MCLK and LRCK are input.
DFS1
0
0
1
DFS0
0
1
0
Sampling Speed (fs)
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Quad Speed Mode
120kHz~192kHz
Default
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920
11.2896
12.2880
MCLK (MHz)
384fs
12.2880
16.9344
18.4320
512fs
16.3840
22.5792
24.5760
BICK (MHz)
64fs
2.0480
2.8224
3.0720
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
fs
88.2kHz
96.0kHz
128fs
11.2896
12.2880
MCLK (MHz)
192fs
16.9344
18.4320
256fs
22.5792
24.5760
BICK (MHz)
64fs
5.6448
6.1440
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
(Note: At Double speed mode(DFS1= “0”, DFS0 = “1”), 128fs and 192fs are not available for ADC.)
LRCK
fs
176.4kHz
192.0kHz
128fs
22.5792
24.5760
MCLK (MHz)
192fs
-
-
256fs
-
-
BICK (MHz)
64fs
11.2896
12.2880
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
(Note: At Quad speed mode(DFS1= “1”, DFS0 = “0”) are not available for ADC.)
MS0385-E-00
- 16 -
2005/02