AK4628A Datasheet, PDF (34/41 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC

ASAHI KASEI
[AK4628A]
Addr Register Name
01H Control 2
Default
D7 D6
D5
D4
D3
D2
D1
D0
0 DFS1 LOOP1 LOOP0 SDOS DFS0 ACKS 0
0
0
0
0
0
0
0
0
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS are
ignored. When this bit is “0”, DFS0, 1 set the sampling speed mode.
DFS1-0: Sampling speed mode (see Table 1.)
Register bit of DFS0 is ORed with DFS0 pin if P/S = “L”.
The setting of DFS is ignored at ACKS bit “1”.
SDOS: SDTO source select
0: ADC
1: DAUX
Register bit of SDOS is ORed with SDOS pin if P/S = “L”.
SDOS should be set to “0” at TDM bit “1”.
In the case of PWADN=”0” and PWDAN=”0”, the setting of SDOS becomes invalid. And ADC is selected.
The output of SDTO becomes “L” at PWADN=”0”.
LOOP1-0: Loopback mode enable
00: Normal (No loop back)
01: LIN → LOUT1, LOUT2, LOUT3, LOUT4
RIN → ROUT1, ROUT2, ROUT3, ROUT4
The digital ADC output (DAUX input if SDOS = “1”) is connected to the digital DAC input. In this
mode, the input DAC data to SDTI1-3 is ignored. The audio format of SDTO at loopback mode
becomes mode 2 at mode 0, and mode 3 at mode 1, respectively.
10: SDTI1(L) → SDTI2(L), SDTI3(L), SDTI4(L)
SDTI1(R) → SDTI2(R), SDTI3(R), SDTI4(R)
In this mode the input DAC data to SDTI2-4 is ignored.
11: N/A
LOOP1-0 should be set to “00” at TDM bit “1”.
In the case of PWADN=”0” and PWDAN=”0”, the setting of LOOP1-0 becomes invalid. And ADC is selected.
And it becomes the normal operation (No loop back).
MS0385-E-00
- 34 -
2005/02